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Conference Paper
Sub-30 nm Gate Template Fabrications for Nanoimprint Lithography using Spacer Patterning Technology
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- Authors
- Kun Sik Park, Kyu Ha Baik, Dong Pyo Kim, Jong Chang Woo, Kwang Soo No, Lee Mi Do
- Issue Date
- 2009-11
- Citation
- International Conference on Nano Science and Nano Technologya (ICNSN) 2009, pp.1-4
- Language
- English
- Type
- Conference Paper
- Abstract
- In this study, we present a spacer patterning technology for sub-30nm gate template which is used for nanoscale MOSFETs fabrications. A spacer patterning technology using a polysilicon layer and a chemical vapor deposition (CVD) spacer layer has been developed, and is demonstrated to achieve sub-30 nm structures with conventional dry etching and chemical mechanical polishing. The minimum-sized features are defined not by the photolithography but by the CVD film thickness. Therefore, this technology yields critical dimension of minimum-sized features much smaller than that achieved by optical or electron beam lithography.
- KSP Keywords
- Chemical Mechanical Polishing(CMP), Chemical Vapor Deposition, Critical dimension, Electron beam lithography, Film thickness, Nanoimprint lithography(NIL), Spacer layer, Sub-30 nm structures, dry etching, nanoscale MOSFETs, patterning technology