상세정보
학술지
A 1.2 V 12b 60 MS/s CMOS Analog Front-End for Image Signal Processing Applications
- 발행일
- 200912
- 출처
- ETRI Journal, v.31 no.6, pp.717-724
- ISSN
- 1225-6463
- 출판사
- 한국전자통신연구원 (ETRI)
- 협약과제
- 09MB2100, 45nm급 혼성 SoC용 아날로그 회로기술, 권종기
- 초록
- This paper describes a 1.2 V 12 b 60 MS/s CMOS analog front-end (AFE) employing low-power and flexible design techniques for image signal processing. An op-amp preset technique and programmable capacitor array scheme are used in a variable gain amplifier to reduce the power consumption with a small area of the AFE. A pipelined analog-to-digital converter with variable resolution and a clock detector provide operation flexibility with regard to resolution and speed. The AFE is fabricated in a 0.13 μm CMOS process and shows a gain error of 0.68 LSB with 0.0352 dB gain steps and a differential/integral nonlinearity of 0.64/1.58 LSB. The signal-to-noise ratio of the AFE is 59.7 dB at a 60 MHz sampling frequency. The AFE occupies 1.73 mm2 and dissipates 64 mW from a 1.2 V supply. Also, the performance of the proposed AFE is demonstrated by an implementation of an image signal processing platform for digital camcorders. Copyright © 2009 ETRI.
- KSP 제안 키워드
- Analog Front-end, Analog to digital converter(ADC), CMOS Process, Capacitor array, Clock detector, Design techniques, Image signal processing, Low-Power, Operation flexibility, Operational Amplifiers(Op-Amps), Pipelined analog-to-digital converter