상세정보
학술지
Effects of ZnO Channel Thickness on the Device Behaviour of Nonvoltile Memory Thin Film Transistor with Double-layered Gate Insulators of Al2O3 and Ferroelectric Polymer
- 발행일
- 200911
- 출처
- Journal of Physics D : Applied Physics, v.42 no.24, pp.1-6
- ISSN
- 0022-3727
- 출판사
- Institute of Physics (IOP)
- 협약과제
- 09MB2900, 투명전자 소자를 이용한 스마트 창, 조경익
- 초록
- Poly(vinylidene fluoride trifluoroethylene) and ZnO were employed for nonvolatile memory thin film transistors as ferroelectric gate insulator and oxide semiconducting channel layers, respectively. It was proposed that the thickness of the ZnO layer be carefully controlled for realizing the lower programming voltage, because the serially connected capacitor by the formation of a fully depleted ZnO channel had a critical effect on the off programming voltage. The fabricated memory transistor with Al/P(VDF-TrFE) (80 nm)/Al 2O3 (4 nm)/ZnO (5 nm) exhibits encouraging behaviour such as a memory window of 3.8 V at the gate voltage of -10 to 12 V, and 10 7 on/off ratio, and a gate leakage current of 10-11 A. © 2009 IOP Publishing Ltd.
- KSP 제안 키워드
- 5 nm, Channel thickness, Double layered, Ferroelectric gate, Fully depleted(FD), Gate insulator, Non-Volatile Memory(NVM), Thin-Film Transistor(TFT), VDF-TrFE, ZnO layer, ferroelectric polymer