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Conference Paper A 4-GHz Low-power TDC-based All Digital PLL having 9.6mW and 1.2ps rms jitter
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Authors
Ja-Yol Lee, Mi-Jeong Park, Seong-Do Kim, Moo-Yang Park, Hyun-Kyu Yu
Issue Date
2011-08
Citation
International Microwave Workshop Series on Intelligent Radio for Future Personal Terminals (IMWS-IRFPT) 2011, pp.1-2
Language
English
Type
Conference Paper
DOI
https://dx.doi.org/10.1109/IMWS2.2011.6027171
Project Code
11MB1500, Development of Advanced Digital RF Technology for Next Generation Wireless Convergence Terminals, Yu Hyun Kyu
Abstract
This paper presents a 4-GHz ADPLL with low-power TDC using two low-rate retimed reference clocks (pCKR, nCKR) to measure the fractional phase error between the reference clock edge and DCO clock edge. The application of the retimed reference clocks enables TDC to avoid metastability of its sampling register as well as alleviate large dynamic power of its delay inverter chain. A mode-decision block is also proposed to generate suitable control signals for accomplishing seamless movement of DCO operation mode. The proposed ADPLL achieves - 95 dBc/Hz in-band phase noise and 1.2ps rms jitter, consuming 9.6mW. © 2011 IEEE.
KSP Keywords
All-digital PLL, Control Signal, Dynamic power, Low-Power, Low-rate, Reference clock, decision block, in-band phase noise, inverter chain, operation mode, phase error