상세정보
학술대회
A 4-GHz Low-power TDC-based All Digital PLL having 9.6mW and 1.2ps rms jitter
- 발행일
- 201108
- 출처
- International Microwave Workshop Series on Intelligent Radio for Future Personal Terminals (IMWS-IRFPT) 2011, pp.1-2
- 협약과제
- 11MB1500, 차세대 무선 융합 단말용 Advanced Digital RF 기술 개발, 유현규
- 초록
- This paper presents a 4-GHz ADPLL with low-power TDC using two low-rate retimed reference clocks (pCKR, nCKR) to measure the fractional phase error between the reference clock edge and DCO clock edge. The application of the retimed reference clocks enables TDC to avoid metastability of its sampling register as well as alleviate large dynamic power of its delay inverter chain. A mode-decision block is also proposed to generate suitable control signals for accomplishing seamless movement of DCO operation mode. The proposed ADPLL achieves - 95 dBc/Hz in-band phase noise and 1.2ps rms jitter, consuming 9.6mW. © 2011 IEEE.
- KSP 제안 키워드
- All-digital PLL, Control Signal, Dynamic power, Low-Power, Low-rate, Operation modes, Reference clock, decision block, in-band phase noise, inverter chain, phase error