ETRI-Knowledge Sharing Plaform



논문 검색
구분 SCI
연도 ~ 키워드


학술지 Memory and Computation Efficient Hardware Design for a 3 Spatial and Temporal Layers SVC Encoder
Cited 1 time in scopus Download 0 time Share share facebook twitter linkedin kakaostory
이규중, 이채은, 이혁재, 강정원
IEEE Transactions on Consumer Electronics, v.57 no.4, pp.1921-1928
10MR2400, 유무선 환경의 개방형 IPTV(IPTV 2.0) 기술개발, 류원
Spatial and temporal scalability in Scalable Video Coding (SVC) compression enables a video encoder to generate bit streams efficiently for various resolutions and frame rates. However, doing this requires more complex computations and greater memory bandwidth than H.264/AVC compression. In this paper, the performance and memory bandwidth for a SVC hardware encoder with three spatial and temporal layers are analyzed. Based on the analysis, a novel method is proposed for the source and interlayer data load. Experimental results show that the memory bandwidth is reduced by 77%. Furthermore, the memory access latency of the source data for the base layer is reduced by creating a data load for the base layer overlap with the execution of the enhancement layer. To satisfy the latency requirement, a mode pre-decision algorithm for a hardware SVC encoder is proposed. It reduces the computation of the fractional motion estimation (FME) and the inter-layer residual prediction by 80%. Simulation results show that the proposed methods decrease the BD-PSNR by 0.05 dB and increase the BD-BR by 1.64%, an amount that can be considered negligible in terms of degradation, while an encoding speed of 30 fps for Full HD (1920-1080) videos is achieved at an operating clock frequency of less than 200 MHz. 1 © 2006 IEEE.
KSP 제안 키워드
Access Latency, An encoding, Base layer, Clock frequency, Decision algorithm, Enhancement layer, Hardware Design, Inter-layer, Memory Access, Memory bandwidth, Motion estimation(ME)