ETRI Knowledge Sharing Platform : A Time-to-Digital Converter Based on a Multiphase Reference Clock and a Binary Counter With a Novel Sampling Error Corrector

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Journal Article A Time-to-Digital Converter Based on a Multiphase Reference Clock and a Binary Counter With a Novel Sampling Error Corrector

Cited 26 time in scopus

Citation: IEEE Transactions on Circuits and Systems II : Express Briefs, v.59, no.3, pp.143-147

Abstract: A new type of sampling error corrector for a time-to-digital converter (TDC) having a multiphase reference clock and a binary counter is demonstrated. With this corrector, sampling errors caused by asynchronous TDC inputs are corrected without requiring additional counters or reclocking circuits. A TDC having the corrector is implemented in 90-nm CMOS logic technology. It has 13.6-ps/least significant bit resolution and 13-bit input dynamic range. It consumes 18 mW from a 1.2-V supply and occupies a 100 × 210 μm 2 chip area. © 2006 IEEE.

KSP Keywords: 90-nm, CMOS logic, Chip area, Least Significant Bit(LSB), Reference clock, Sampling error, Time-to-Digital Converter, binary counter, dynamic range, logic technology, new type

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