상세정보
학술지
A 10-bit 30-MS/s Successive Approximation Register Analog-to-Digital Converter for Low-Power Sub-Sampling Applications
- 발행일
- 201112
- 출처
- Microelectronics Journal, v.42 no.12, pp.1335-1342
- ISSN
- 0026-2692
- 출판사
- Elsevier
- 협약과제
- 11MI1900, 차세대 이동통신 기지국용 Class-S 전력증폭기 기술 연구, 정재호
- 초록
- A 10-bit 30-MS/s successive approximation register analog-to-digital converter (ADC), which is suitable for low-power sub-sampling applications, is presented. Bootstrapped switches are used to enhance the sampling linearity at the high input frequency. The proposed ADC adopts a binary-weighted split-capacitor array with the energy efficient switching procedure and includes an asynchronous clock scheme to yield more power and speed-efficiency. The ADC is fabricated in a 65 nm complementary metal-oxide-semiconductor technology and occupies an active area of 0.07 mm2. The differential and integral nonlinearities of the ADC are less than 0.82 and 1.13 LSB, respectively. The ADC shows a signal-to-noise-distortion ratio of 56.60 dB, a spurious free dynamic range of 73.35 dB, and an effective number of bits (ENOB) of 9.11-bits with a 2.5-MHz sinusoidal input at 30-MS/s. It exhibits higher than 8.86 ENOB for input frequencies up to 78-MHz. The ADC consumes 0.85 mW at a 1.1 V supply and achieves a figure-of-merit of 51 fJ/conversion-step. © 2011 Elsevier Ltd. All rights reserved.
- KSP 제안 키워드
- 65 nm, 7 mm, Active area, Analog to digital converter(ADC), Asynchronous clock, Capacitor array, Clock scheme, Complementary metal-oxide-semiconductor(CMOS), Distortion ratio, Effective Number of Bits, Figure of merit