상세정보
학술지
A 12-Bit 200-MS/s Pipelined A/D Converter with Sampling skew Reduction Technique
- 발행일
- 201111
- 출처
- Microelectronics Journal, v.42 no.11, pp.1225-1230
- ISSN
- 0026-2692
- 출판사
- Elsevier
- 협약과제
- 10MB1700, 45nm급 혼성 SoC용 아날로그 회로기술, 권종기
- 초록
- This paper presents a 12-bit 200-MS/s dual channel pipeline analog-to-digital converter (ADC). The ADC is featured with a digital timing correction for reducing a sampling skew and the capacitor swapping for suppressing nonlinearities at the first stage in the pipelined ADC. The prototype ADC occupies 0.8×1.4 mm2 in a 65-nm CMOS technology. The differential nonlinearity is less than 1.0 least significant bit with a 200 MHz sampling frequency. With a sampling frequency of a 200-MS/s and an input of a 2.4 MHz, the ADC, respectively, achieves a signal to noise-and-distortion ratio and a spurious-free dynamic range of 61.49 dB70.71 dB while consuming of 112 mW at a supply voltage of 1.1 V. © 2011 Elsevier Ltd.
- KSP 제안 키워드
- A/D converter, Analog to digital converter(ADC), CMOS Technology, Distortion ratio, First stage, Least Significant Bit(LSB), Pipelined ADC, Reduction technique, Sampling frequency, Signal-to-Noise, Supply voltage