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A 12-Bit 200-MS/s Pipelined A/D Converter with Sampling skew Reduction Technique
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- Authors
- Jae-Won Nam, Young-Deuk Jeon, Young-Kyun Cho, Jong-Kee Kwon
- Issue Date
- 2011-11
- Citation
- Microelectronics Journal, v.42, no.11, pp.1225-1230
- ISSN
- 0026-2692
- Publisher
- Elsevier
- Language
- English
- Type
- Journal Article
- Abstract
- This paper presents a 12-bit 200-MS/s dual channel pipeline analog-to-digital converter (ADC). The ADC is featured with a digital timing correction for reducing a sampling skew and the capacitor swapping for suppressing nonlinearities at the first stage in the pipelined ADC. The prototype ADC occupies 0.8×1.4 mm2 in a 65-nm CMOS technology. The differential nonlinearity is less than 1.0 least significant bit with a 200 MHz sampling frequency. With a sampling frequency of a 200-MS/s and an input of a 2.4 MHz, the ADC, respectively, achieves a signal to noise-and-distortion ratio and a spurious-free dynamic range of 61.49 dB70.71 dB while consuming of 112 mW at a supply voltage of 1.1 V. © 2011 Elsevier Ltd.
- KSP Keywords
- A/D converter, Analog to digital converter(ADC), CMOS Technology, Distortion ratio, First stage, Least Significant Bit(LSB), Pipelined ADC, Reduction technique, Sampling frequency, Signal-to-Noise, Supply voltage