상세정보
학술지
A compact memory-free architecture for the AES algorithm using resource sharing methods
- 저자
- 전용성, 김영진, 이동호
- 발행일
- 201008
- 출처
- Journal of Circuits, Systems and Computers, v.19 no.5, pp.1109-1130
- ISSN
- 0218-1266
- 출판사
- World Scientific Publishing
- 협약과제
- 10MS3400, 개인신변 안전보장을 위한 영상보안 기술개발, 한종욱
- 초록
- This paper presents a resource-shared 8-bit (RS8) architeture for the AES algorithm, which aims at compacting the hardware architecture and allows hardware resources to be shared efficiently between encryption and decryption without using a memory. The RS8 architecture only requires one combined S-box/S-1-box for encryption, decryption and key expansion. The RS8 architecture implements the multiplicative inverse in the composite field GF((24)2) with resource sharing methods. In addition, the number of XOR gates used by the proposed combined MixColumns/InvMixColumns module is less than half that of the conventional 32-bit architecture. When comparing the RS8 architecture with the conventional 32-bit architecture on a Xilinx Spartan2 FPGA, the number of total equivalent slices is reduced by 51%. Additionally, the highest operation frequency of the RS8 architecture is 66 MHz, and the throughput is 24 Mbps. Therefore, the performance of the RS8 architecture is sufficient for low-area applications such as wireless network devices and radio frequency identification (RFID). © 2010 World Scientific Publishing Company.
- KSP 제안 키워드
- 6 MHz, AES Algorithm, First Stokes(S1), Hardware Architecture, Hardware Resources, Multiplicative Inverse, Network devices, Passive radio frequency identification(RFID), Radio Frequency(RF), Resource sharing methods, S-box