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학술지 A Fully Integrated High Efficiency RF Power Amplifier for WLAN Application in 40 nm Standard CMOS Process
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저자
유남식, 박봉혁, 정용채
발행일
201506
출처
IEEE Microwave and Wireless Components Letters, v.25 no.6, pp.382-384
ISSN
1531-1309
출판사
IEEE
DOI
https://dx.doi.org/10.1109/LMWC.2015.2421351
협약과제
14MI8100, 밀리미터파 5G 이동통신 시스템 개발, 김태중
초록
This paper proposes a CMOS linear power amplifier (PA) design scheme for IEEE 802.11g (WLAN) application. The proposed PA consists of a programmable gain amplifier and a high power stage which is composed of a main amplifier with class AB bias and an auxiliary amplifier with class C bias. Based on the un-even bias scheme, the power stage can improve linearity and reduce current consumption in the low power region. It is fabricated with a TSMC 40 nm standard RF CMOS process. The measurements show that the designed PA reaches a 1 dB gain compression output power of 24.6 dBm and a peak drain efficiency of 38% with a 3.3 V power supply at 2.4 GHz operating frequency range. When the PA was tested with an IEEE 802.11g OFDM signal of 20 MHz channel bandwidth, the obtained -25 dB EVM compliant output power and drain efficiency are 18.5 dBm and 14%, respectively.
키워드
CMOS power amplifier, efficiency enhancement, high efficiency, linear power amplifier, linearization, OFDM, WLAN
KSP 제안 키워드
2.4 GHz, 3 V, 40 nm, Bias scheme, CMOS power amplifier, Channel bandwidth, Class AB(CAB), Class-C, Current consumption, Design Scheme, Fully integrated