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High-Speed Architecture for K-Dimensional LFSR in H/W Implementation
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- Authors
- Chan-Bok Jeong, Dae-Ho Kim, Hyeon-Deok Bae
- Issue Date
- 2011-08
- Citation
- International Midwest Symposium on Circuits and Systems (MWSCAS) 2011, pp.1-4
- Language
- English
- Type
- Conference Paper
- Abstract
- Proposal for a high-speed architecture of Linear Feedback Shift Registers (LFSR), related to the hardware implementation of pseudo-random Gold-sequence, is presented here. In high-speed communication systems, a scrambling of large coded bits is difficult to compute using a conventional LFSR architecture because the requested processing time for scrambling function is very increased in proportion to length of a data stream. In this paper, we investigate the use of VLSI technology to speed up scrambling block and propose a novel LFSR architecture by generalizing an analysis of the researched architecture. The analysis of the proposed LFSR architecture demonstrates that the proposed k-dimensional LFSR architecture is k times as fast as a conventional LFSR architecture and the used processing time for scrambling is enough to implement scramble function for high-speed applications such as LTE-Advanced. © 2011 IEEE.
- KSP Keywords
- Communication system, Data stream, Hardware implementation, LTE-Advanced, Linear feedback shift registers(LFSR), Pseudo-random, Speed-up, high-speed communication, processing time