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학술대회 High-Speed Architecture for K-Dimensional LFSR in H/W Implementation
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저자
정찬복, 김대호, 배현덕
발행일
201108
출처
International Midwest Symposium on Circuits and Systems (MWSCAS) 2011, pp.1-4
DOI
https://dx.doi.org/10.1109/MWSCAS.2011.6026568
협약과제
11VI1100, 스마트 모바일 서비스를 위한 B4G 이동통신 기술 개발, 박남훈
초록
Proposal for a high-speed architecture of Linear Feedback Shift Registers (LFSR), related to the hardware implementation of pseudo-random Gold-sequence, is presented here. In high-speed communication systems, a scrambling of large coded bits is difficult to compute using a conventional LFSR architecture because the requested processing time for scrambling function is very increased in proportion to length of a data stream. In this paper, we investigate the use of VLSI technology to speed up scrambling block and propose a novel LFSR architecture by generalizing an analysis of the researched architecture. The analysis of the proposed LFSR architecture demonstrates that the proposed k-dimensional LFSR architecture is k times as fast as a conventional LFSR architecture and the used processing time for scrambling is enough to implement scramble function for high-speed applications such as LTE-Advanced. © 2011 IEEE.
KSP 제안 키워드
Communication system, Data stream, Hardware Implementation, High Speed Communication, LTE-Advanced, Linear feedback shift register, Pseudo-random, Speed-up, processing time