상세정보
학술지
A 2GHz Synthesized Fractional-N ADPLL With Dual-Referenced Interpolating TDC
- 발행일
- 201602
- 출처
- IEEE Journal of Solid-State Circuits, v.51 no.2, pp.391-400
- ISSN
- 0018-9200
- 출판사
- IEEE
- 협약과제
- 15MI2100, (통합)초연결 스마트 모바일 서비스를 위한 5G 이동통신 핵심기술개발, 정현규
- 초록
- This paper presents a synthesized 2 GHz fractional-N ADPLL with a dual-referenced interpolating time-to-digital converter (TDC). The proposed TDC measures fractional phase by referencing adjacent two integer phases and achieves gain matching without any calibration scheme. It also improves linearity with little sensitivity to process, voltage, and temperature variations by averaging nonlinearity errors of opposite polarities. Except for digitally controlled oscillator (DCO), the PLL is designed only by RTL-level behavioral descriptions and synthesized with a standard cell library. The PLL is implemented in 65 nm CMOS with an active area of 0.047 mm2 and achieves a stable in-band phase noise of lower than -100 dBc/Hz in a wide range of supply voltage from 1 to 1.4 V.
- KSP 제안 키워드
- 65nm CMOS, 7 mm, Active area, Digitally controlled oscillator, Sensitivity to, Standard cell library, Supply voltage, Temperature variations, Time-to-Digital Converter, Wide range, fractional-n