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A 2 GHz Synthesized Fractional-N ADPLL With Dual-Referenced Interpolating TDC
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- Authors
- Shinwoong Kim, Seunghwan Hong, Kapseok Chang, Hyungsik Ju, Jaewook Shin, Byungsub Kim, Hong-June Park, Jae-Yoon Sim
- Issue Date
- 2016-02
- Citation
- IEEE Journal of Solid-State Circuits, v.51, no.2, pp.391-400
- ISSN
- 0018-9200
- Publisher
- IEEE
- Language
- English
- Type
- Journal Article
- Abstract
- This paper presents a synthesized 2 GHz fractional-N ADPLL with a dual-referenced interpolating time-to-digital converter (TDC). The proposed TDC measures fractional phase by referencing adjacent two integer phases and achieves gain matching without any calibration scheme. It also improves linearity with little sensitivity to process, voltage, and temperature variations by averaging nonlinearity errors of opposite polarities. Except for digitally controlled oscillator (DCO), the PLL is designed only by RTL-level behavioral descriptions and synthesized with a standard cell library. The PLL is implemented in 65 nm CMOS with an active area of 0.047 mm2 and achieves a stable in-band phase noise of lower than -100 dBc/Hz in a wide range of supply voltage from 1 to 1.4 V.
- KSP Keywords
- 65nm CMOS, 7 mm, Active area, Digitally controlled oscillator, Sensitivity to, Standard cell library, Supply voltage, Temperature variations, Time-to-Digital Converter, fractional-n, in-band phase noise