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Pre-Silicidation Annealing Effect on Platinum-Silicided Schottky Barrier MOSFETs
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- Authors
- Myungsim Jun, Chel-Jong Choi, Sung-Jin Choi, Youngsam Park, Younghoon Hyun, Taehyoung Zyung, Moongyu Jang
- Issue Date
- 2011-12
- Citation
- Semiconductor Science and Technology, v.26, no.12, pp.1-4
- ISSN
- 0268-1242
- Publisher
- Institute of Physics (IOP)
- Language
- English
- Type
- Journal Article
- Abstract
- We fabricated platinum-silicided p-type Schottky barrier MOSFETs (SB-MOSFETs) with 40 nm gate length on a silicon-on-insulator wafer. In order to improve the device performance, the devices were annealed at a temperature of 900 °C in a nitrogen environment prior to the platinum deposition for source/drain silicide formation. As a result, lowered threshold voltage of 1.2 V, subthreshold swing values of 110 mV and an enhanced on/off current ratio larger than 107 were obtained. This improvement is attributed to the reduction of the fixed oxide charge in the gate oxide during the annealing process. © 2011 IOP Publishing Ltd.
- KSP Keywords
- 40 nm, Annealing effects, Gate oxide, Platinum deposition, Schottky barrier, Silicide formation, Silicon On Insulator(SOI), annealing process, device performance, gate length, on/off current ratio