상세정보
학술지
Design of Parasitic Inductance Reduction in GaN Cascode FET for High-Efficiency Operation
- 발행일
- 201602
- 출처
- ETRI Journal, v.38 no.1, pp.133-140
- ISSN
- 1225-6463
- 출판사
- 한국전자통신연구원 (ETRI)
- 협약과제
- 15MB1500, 스마트 데이터센터용 차세대 광-전 모듈 기술, 남은수
- 초록
- This paper presents a method of parasitic inductance reduction for high-speed switching and high-efficiency operation of a cascode structure with a low-voltage enhancement-mode silicon (Si) metal-oxide- semiconductor field-effect transistor (MOSFET) and a high-voltage depletion-mode gallium nitride (GaN) fieldeffect transistor (FET). The method is proposed to add a bonding wire interconnected between the source electrode of the Si MOSFET and the gate electrode of the GaN FET in a conventional cascode structure package to reduce the most critical inductance, which provides the major switching loss for a high switching speed and high efficiency. From the measured results of the proposed and conventional GaN cascode FETs, the rising and falling times of the proposed GaN cascode FET were up to 3.4% and 8.0% faster than those of the conventional GaN cascode FET, respectively, under measurement conditions of 30 V and 5 A. During the rising and falling times, the energy losses of the proposed GaN cascode FET were up to 0.3% and 6.7% lower than those of the conventional GaN cascode FET, respectively.
- KSP 제안 키워드
- Bonding wires, Field-effect transistors(FETs), GaN FET, High Voltage, Major switching, Metal-oxide(MOX), Parasitic inductance, Switching Loss, cascode structure, critical inductance, depletion mode