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Conference Paper
Integrated Parallel Scrambler Design for High-speed Transmission Systems
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- Authors
- S.H. Lee, P.J. Lee
- Issue Date
- 1988-06
- Citation
- International Symposium on Circuits and Systems 1988, pp.361-364
- Language
- English
- Type
- Conference Paper
- Abstract
- A general parallel scrambling procedure based on exact relationships between high-speed and low-speed m-sequences is described. In particular, a novel implementation scheme using only one pure-cycling shift register without any exclusive-OR (XOR) gate in the feedback loop for generating the parallel scrambling sequences is presented. The use of a crosspoint switch in this method makes it applicable to a selectable multiplexing factor, thereby enabling the design of a general-purpose parallel scrambling circuit.
- KSP Keywords
- Crosspoint Switch, Feedback Loop, High-speed transmission, Implementation scheme, Pseudo-random sequence(M-sequence), Shift Register, Transmission system, exclusive or(XOR), low speed