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학술지 Circuit Emulations
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저자
C. K. Kim, 이상훈, L. T. Wu
발행일
198810
출처
International Journal of Digital and Analog Cabled Systems, v.1 no.4, pp.245-256
ISSN
1074-5351
DOI
https://dx.doi.org/10.1002/dac.4520010411
초록
The deployment of broadband public packet networks requires integrating packet technology into the larger, predominantly circuit?릗witched world. In this paper, we translate the need for circuit?릗witched network compatibility into a class of packet transport capabilities referred to as circuit emulations. We first present our initial estimates of performance goals for emulating circuit?릗witched connections in a broadband packet network. To show the feasibility of this new networking approach, we then describe a switch design capable of satisfying the stringent packet loss rate and delay requirements for emulating circuits at the DS1 rate and above. Finally, we demonstrate the ability to reconstruct continuous signals from emulated circuits using a simple time?륾veraging clock recovery scheme based on a computer simulation model. Copyright © 1988 John Wiley & Sons, Ltd.
KSP 제안 키워드
Clock recovery(CR), Computer simulation(MC and MD), Computer simulation model, Packet networks, Packet transport, Switch Design, need for, packet loss rate, recovery scheme