상세정보
학술지
Design of a Clockless MSP430 Core using Mixed Asynchronous Design Flow
- 발행일
- 201703
- 출처
- IEICE Electronics Express, v.14 no.8, pp.1-12
- ISSN
- 1349-2543
- 출판사
- 일본, 전자정보통신학회 (IEICE)
- 초록
- There are various limitations on the supporting tools and design methodologies for the implementation of an asynchronous delay-insensitive model. In this paper, we propose a new design flow by exploiting a mixed model, which combines a bounded delay model and a delay-insensitive model. To develop the design flow, we use an asynchronous finite-state machine for the bounded delay model and the null convention logic for the delay-insensitive model. Further, we designed an MSP430 core to verify the proposed design flow and the results of simulation show that it exhibits a performance improvement of 30.34% over its synchronous counterpart.
- KSP 제안 키워드
- Bounded delay, Delay model, Delay-insensitive, Design flow, Mixed model, Supporting tools, asynchronous design, design methodology, finite state machine, null convention logic, performance improvement