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Detail
Journal Article
Wire Optimization and Delay Reduction for High-Performance on-Chip Interconnection in GALS Systems
- Authors
- Myeong-Hoon Oh, Young Woo Kim, Hag Young Kim, Young-Kyun Kim, Jin-Sung Kim
- Issue Date
- 2017-08
- Citation
- ETRI Journal, v.39, no.4, pp.582-591
- ISSN
- 1225-6463
- Publisher
- 한국전자통신연구원 (ETRI)
- Language
- English
- Type
- Journal Article
- Abstract
- To address the wire complexity problem in largescale globally asynchronous, locally synchronous systems, a current-mode ternary encoding scheme was devised for a two-phase asynchronous protocol. However, for data transmission through a very long wire, few studies have been conducted on reducing the long propagation delay in current-mode circuits. Hence, this paper proposes a current steering logic (CSL) that is able to minimize the long delay for the devised current-mode ternary encoding scheme. The CSL creates pulse signals that charge or discharge the output signal in advance for a short period of time, and as a result, helps prevent a slack in the current signals. The encoder and decoder circuits employing the CSL are implemented using 0.25-lm CMOS technology. The results of an HSPICE simulation show that the normal and optimal mode operations of the CSL achieve a delay reduction of 11.8% and 28.1%, respectively, when compared to the original scheme for a 10-mm wire. They also reduce the power-delay product by 9.6% and 22.5%, respectively, at a data rate of 100 Mb/s for the same wire length.
- KSP Keywords
- CMOS Technology, Current steering, Current-mode(CM), Current-mode circuits, Data transmission, Encoder and Decoder, Globally Asynchronous, HSPICE simulation, High performance, Locally Synchronous, Long propagation delay
This work is distributed under the term of Korea Open Government License (KOGL)
(Type 4: : Type 1 + Commercial Use Prohibition+Change Prohibition)
(Type 4: : Type 1 + Commercial Use Prohibition+Change Prohibition)
