상세정보
학술지
A Dual-Channel Pipelined ADC with Sub-ADC Based on Flash-SAR Architecture
- 발행일
- 201211
- 출처
- IEEE Transactions on Circuits and Systems II : Express Briefs, v.59 no.11, pp.741-745
- ISSN
- 1549-7747
- 출판사
- IEEE
- 협약과제
- 10MB1700, 45nm급 혼성 SoC용 아날로그 회로기술, 권종기
- 초록
- This brief presents a 10-bit dual-channel pipelined flash-successive approximation register (SAR) analog-to-digital converter (ADC) for high-speed applications. The proposed ADC consists of two channels for high operating speed, and each channel adopts a pipelined flash-SAR architecture for low power and a small area. The proposed flash-SAR ADC in the second stage is composed of a 1-bit flash ADC and a 6-bit SAR ADC considering the chip area, operation speed, and circuit complexity. The prototype ADC fabricated in a 45-nm CMOS process occupies 0.16 mm2. The differential and integral nonlinearities of the ADC are less than 0.36 and 0.67 LSB, respectively. The ADC shows a signal-to-noise-and-distortion ratio of 54.6 dB and a spurious-free dynamic range of 64.0 dB with a 78-MHz input at 230 MS/s with a 1.1-V supply. The maximum operating frequency of the ADC is 260 MS/s at a 1.2-V supply. The power consumptions of the ADC with 230 and 260 MS/s are 13.9 and 17.8 mW, respectively. © 2004-2012 IEEE.
- KSP 제안 키워드
- 45-nm CMOS process, Analog to digital converter(ADC), Chip area, Circuit complexity, Distortion ratio, High Speed, Low-Power, Operating speed, Operation speed, Pipelined ADC, Power Consumption