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Conference Paper Power Estimation of Cryptographic Modules using Virtual SoC Platform
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Authors
Sung Jae Yoon, Park Ki Hyuk, Kim Wonjong, Cho Han Jin
Issue Date
201801
Source
International Conference on Electronics, Information and Communication (ICEIC) 2018, pp.1098-1100
DOI
https://dx.doi.org/10.23919/ELINFOCOM.2018.8330655
Project Code
17ZT1100, Pangyo TechnoValley Related Open SW-SoC Convergence Platform Development, Lim Deok Rae
Abstract
The power consumption in cryptographic modules depends on hardware and software. The virtual SoC platform is a good candidate for co-designing them together and to estimate performance and power consumption. We proposed the method to estimate power consumption of the cryptographic modules using virtual SoC platform. The power consumption of cryptographic modules depends on the status of each cryptographic module. To minimize the increase in simulation time, we only consider the changes of state registers. The experimental results show that the power estimation of cryptographic modules can be estimated with reasonable error bounding using the proposed method.
KSP Keywords
Co-designing, Cryptographic module, Error bounding, Power Consumption, hardware and software, power estimation, simulation time