상세정보
학술지
A Low-Power Continuous-Time Delta-Sigma Modulator Using a Resonant Single Op-Amp Third-Order Loop Filter
- 발행일
- 201807
- 출처
- IEEE Transactions on Circuits and Systems II : Express Briefs, v.65 no.7, pp.854-858
- ISSN
- 1549-7747
- 출판사
- IEEE
- 협약과제
- 17HF1400, 차세대 무선통신용 반도체 기반 스마트 안테나 기술 개발, 현석봉
- 초록
- A third-order loop filter (LF) using a single op-amp resonator is presented for continuous-time delta-sigma modulators. The proposed technique improves both the power and area efficiencies by reducing the number of active components and simplifying the modulator topology. It also enhances the controllability of the transfer function and resonating condition of the single op-amp LF by using positive feedback. A more power-efficient implementation is obtained with an autonomous common-mode dynamic comparator. Fabricated in a 180-nm CMOS technology, the modulator occupies an active area of 0.14 mm2 and consumes 37.4-μW power from a 1.8-V supply. It achieves a dynamic range of 72.5 dB and a peak signal-to-noise and distortion ratio of 67.3 dB in a 150-kHz signal bandwidth when clocked at 12 MHz. The Walden figure-of-merit of the modulator is 65.9 fJ/conv.-step.
- KSP 제안 키워드
- 180-nm CMOS, Active area, Active components, CMOS Technology, Continuous-time delta-sigma modulator, Distortion ratio, Dynamic Comparator, Figure of merit, Low-Power, Operational Amplifiers(Op-Amps), Positive Feedback