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Visible Light-Erasable Oxide FET-Based Nonvolatile Memory Operated with a Deep Trap Interface
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- Authors
- Taeyoon Kim, Jung Wook Lim, Seong Hyun Lee, Jeho Na, Jiwoon Jeong, Kwang Hoon Jung, Gayoung Kim, Sun Jin Yun
- Issue Date
- 2018-08
- Citation
- ACS Applied Materials & Interfaces, v.10, no.31, pp.26405-26412
- ISSN
- 1944-8244
- Publisher
- American Chemical Society(ACS)
- Language
- English
- Type
- Journal Article
- Abstract
- A new concept of a tunneling oxide-free nonvolatile memory device with a deep trap interface floating gate is proposed. This device demonstrates a high on/off current ratio of 107 and a sizable memory window due to deep traps at the interface between the channel and gate dielectric layers. Interestingly, irradiation with 400 nm light can completely restore the program state to the initial one (performing an erasing process), which is attributed to the visible light-sensitive channel layer. Device reproducibility is enhanced by selectively passivating shallow traps at the interface using in situ H2 plasma treatment. The passivated memory device shows highly reproducible memory operation and on-state current during retention bake tests at 85 °C. One of the most significant advantages of this visible light-erasable oxide field-effect transistor-based nonvolatile memory is its simple structure, which is free from deterioration due to the frequent tunneling processes, as compared to conventional nonvolatile memory devices with tunneling oxides.
- KSP Keywords
- AND gate, Channel layer, Deep traps, Field-effect transistors(FETs), Floating gate, Light-sensitive, Non-Volatile Memory(NVM), Nonvolatile memory devices, ON/OFF current ratio, Oxide field, Oxide-free