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학술지 84% High Efficiency Dynamic Voltage Scaler with Nano-Second Settling Time based on Charge-Pump and BWC-DAC
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저자
A.N. Ragheb, 김형원, 이재진
발행일
201809
출처
Microelectronics Journal, v.79, pp.919-97
ISSN
0026-2692
출판사
Elsevier
DOI
https://dx.doi.org/10.1016/j.mejo.2018.06.012
협약과제
18ZB1200, 임플란터블 능동 전자소자 원천기술 개발, 이정익
초록
This paper introduces an energy-efficient dynamic voltage scaler (DVS) based on charge- pump and binary-weighted capacitor digital to analog converter (BWC-DAC). Conventional DVS architectures suffer from long settling-time beside the limitation of coarse voltage resolution, so we propose DVS architecture based on BWC-DAC architecture. It takes advantage of DAC's reconfigurable structure to provide an output voltage scaled with high resolution of VIN/2N for input voltage VIN and N configuration bits; and Nano-second transition time. However, DAC inherently suffers from low power efficiency because it requires frequent reset to maintain the output voltage. To overcome this issue, a high efficiency charge-pump is employed to restore the charges in DAC's capacitors without the need to reset which results in improved power efficiency. The proposed DVS with a 6-bit DAC and a feedback controlled circuit have been implemented using a 130 nm CMOS process. The measurement results show an accurate 64 voltage levels of the 6-bit DAC from 0 V to 1.476 V, when supplied by an input voltage of 1.5 V. We achieved a peak efficiency of 84% for load current ranging from 1 μA??14.76 μA. Furthermore, it provides an extremely short settling time that is as short as 83.6 Nano second.
KSP 제안 키워드
130 nm, CMOS Process, Charge pump, High-resolution, Input voltage, Load current, Low-Power, Nano second, Output Voltage, Peak efficiency, Power Efficiency