상세정보
학술지
TEI-ULP: Exploiting Body Biasing to Improve the TEI-Aware Ultra-Low Power Methods
- 발행일
- 201909
- 출처
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, v.38 no.9, pp.1758-1770
- ISSN
- 0278-0070
- 출판사
- IEEE
- 협약과제
- 18ZB1200, 임플란터블 능동 전자소자 원천기술 개발, 이정익
- 초록
- Temperature effect inversion (TEI) phenomenon in ultralow power (ULP) very large scale integration circuits has been identified as an important effect by both academia and industry. Although a number of ULP methods that attempt to exploit the TEI phenomenon have been proposed, the small size of the design exploration space when applying these methods to ULP circuits hinders them from achieving their full potential. This is mainly due to the limited granularity of the supply voltage level control. Starting with an intuition that the body biasing (BB) technique is a key to overcome this limitation, this paper exploits the BB technique along with the TEI-aware voltage scaling (TEI-VS) method and TEI-aware frequency scaling (TEI-FS) method, so as to substantially increase the design spaces of these methods. Techniques for optimally combining the BB technique with TEI-VS and TEI-FS are introduced. Simulation results with the latest commercial CMOS process technologies for ULP designs demonstrate the effectiveness of the proposed methodology.
- KSP 제안 키워드
- Body Biasing, CMOS Process, Design Exploration, Design spaces, Supply voltage, Temperature effect inversion(TEI), Ultralow power(ULP), Very Large Scale Integration(VLSI), Voltage scaling, frequency scaling, level control