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학술대회 Design of 6-bit 28GHz Phase Shifter in 65nm CMOS
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저자
박지훈, 공선우, 장승현, 이희동, 김광선, 이광천
발행일
201811
출처
Asia-Pacific Microwave Conference (APMC) 2018, pp.1-3
DOI
https://dx.doi.org/10.23919/APMC.2018.8617563
협약과제
18HF1500, 5G 이동통신용 밀리미터파(40GHz 이하) 빔포밍 부품 개발, 김광선
초록
This paper presents a 6-bit 28GHz phase shifter in 65nm CMOS technology. The phase shifter is composed of switching-type phase shifters to achieve low power consumption, low insertion loss, and bidirectionality. The relative phase shift varies from 0째 to 354.375째 with a step of 5.625째. The result of EM simulation shows that the phase shifter has the insertion loss less than 8.63dB over a frequency range of the 26.5 to 29.5GHz. The return loss is smaller than -10.5dB and the RMS phase error is 3.11째. The core size of the phase shifter is 0.38×0.98mm.
KSP 제안 키워드
65nm CMOS technology, Core size, EM simulation, Frequency Range, Phase Shifter, Relative phase shift, Return loss(RL), low insertion loss, low power consumption, phase error