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Conference Paper
Design of Analog and Digital Hybrid MAC Circuit for Artificial Neural Networks
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- Authors
- Ki-Hyuk Park, Min-Hyung Cho, Young-Deuk Jeon, Joo-Hyun Lee
- Issue Date
- 2019-01
- Citation
- International Conference on Electronics, Information and Communication (ICEIC) 2019, pp.621-623
- Language
- English
- Type
- Conference Paper
- Project Code
- 18HB2200, Brain-Inspired Neuromorphic Perception and Learning Processor, Lee Joo Hyun
- Abstract
- Demand for high-performance hardware acceleration for machine learning applications is increasing rapidly. This paper presents a low power analog and digital hybrid MAC (Multiply and Accumulation) circuit for artificial neural networks. The proposed MAC circuit consists of an analog synapse unit, digital preprocessing and postprocessing unit for support of the parallel analog synapse cores. As the hybrid MAC circuit supports relatively low power and fast multiple MAC operations, it provides a good advantage in developing hardware accelerator for artificial neural networks.
- KSP Keywords
- Artificial Neural Network, Hardware accelerator, High performance, Hybrid MAC, hardware acceleration, low power analog, machine learning applications