상세정보
학술지
Implementation of FPGA-based MPLS-TP Linear Protection Switching for 4000+ Tunnels in Packet Transport Network for Optical Carrier Ethernet
- 발행일
- 201903
- 출처
- IET Communications, v.13 no.5, pp.481-488
- ISSN
- 1751-8628
- 출판사
- IET
- 협약과제
- 18HH2400, Photonic Frame 기반 패킷 스위칭 가능한 데이터 센터 광 네트워킹 핵심 기술 개발, 김광준
- 초록
- A packet transport network (PTN) for optical carrier Ethernet needs to be reliable even in a case that a fault occurs on a data path. To survive from the network fault, protection switching which sends data traffic to a pre-established backup path can be implemented on optical PTN systems. Linear protection switching in a multi-protocol label switching - transport profile (MPLS-TP) environment requires to be performed with sub-50 ms for multiple faults on data paths (i.e. tunnels). The linear protection switching for the recovery from multiple faults at almost ten tunnels can be processed on CPU. In this study, a packet transport layer protection switching integrated circuit (PPSI) is developed to increase the number of multiple protection switchings (e.g. 4000+ tunnels) with satisfying the strict requirement on sub-50 ms switching time, by processing on a field-programmable gate array (FPGA). The performance of this FPGA implementation is compared with that of the processed on CPU. Furthermore, this study investigates four message forwarding methods of set-bridge-and-selector and automatic protection coordination protocol messages to enhance the performance of the PPSI. The four methods are evaluated using an FPGA test-bed, in terms of switching time and the number of tunnels.
- KSP 제안 키워드
- Backup path, Coordination protocol, Data traffic, FPGA Implementation, Field Programmable Gate Arrays(FPGA), Integrated circuit, MPLS-TP, Message forwarding, Multi-Protocol Label Switching, Optical Carrier Ethernet, Protection switching