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학술지 A Diagnosable Network-on-Chip for FPGA Verification of Intellectual Properties
Cited 4 time in scopus Download 8 time Share share facebook twitter linkedin kakaostory
저자
한규승, 이재진, 이우주, 이진호
발행일
201904
출처
IEEE Design & Test, v.36 no.2, pp.81-87
ISSN
2168-2356
출판사
IEEE
DOI
https://dx.doi.org/10.1109/MDAT.2018.2890238
협약과제
18HB2600, 경량 RISC-V 기반 초저전력 인텔리전트 엣지 지능형반도체 기술 개발, 이재진
초록
Editor's note: Debug and validation are important steps required to ensure that systems-on-chip satisfies the design specs. This article presents an elegant diagnosis technique integrated within the network-on-chip infrastructure. The authors demonstrate the proposed technique on an FPGA prototype.-Umit Y. Ogras, Arizona State University
KSP 제안 키워드
FPGA prototype, Intellectual property(IP), Network on Chip(NoC), State university, Systems-on-Chip, on-chip infrastructure