BROWSE
Detail
Journal Article
A Diagnosable Network-on-Chip for FPGA Verification of Intellectual Properties
Cited 4 time in 
Share 
Share
- Authors
- Kyuseung Han, Jae-Jin Lee, Woojoo Lee, Jinho Lee
- Issue Date
- 2019-04
- Citation
- IEEE Design & Test, v.36, no.2, pp.81-87
- ISSN
- 2168-2356
- Publisher
- IEEE
- Language
- English
- Type
- Journal Article
- Abstract
- Editor's note: Debug and validation are important steps required to ensure that systems-on-chip satisfies the design specs. This article presents an elegant diagnosis technique integrated within the network-on-chip infrastructure. The authors demonstrate the proposed technique on an FPGA prototype.-Umit Y. Ogras, Arizona State University
- KSP Keywords
- FPGA prototype, Intellectual property(IP), Network on Chip(NoC), State university, Systems-on-Chip, on-chip infrastructure