상세정보
학술대회
Function-Safe Vehicular AI Processor with Nano Core-In-Memory Architecture
- 발행일
- 201903
- 출처
- International Conference on Artificial Intelligence Circuits and Systems (AICAS) 2019, pp.127-131
- 협약과제
- 18HB2800, 인공지능프로세서 전문연구실, 권영수
- 초록
- State-of-the-art neural network accelerators consist of arithmetic engines organized in a mesh structure datapath surrounded by memory blocks that provide neural data to the datapath. While server-based accelerators coupled with server-class processors are accommodated with large silicon area and consume large amounts of power, electronic control units in autonomous driving vehicles require power-optimized, 'AI processors' with a small footprint. An AI processor for mobile applications that integrates general-purpose processor cores with mesh-structured neural network accelerators and high speed memory while achieving high-performance with low-power and compact area constraints necessitates designing a novel AI processor architecture. We present the design of an AI processor for electronic systems in autonomous driving vehicles targeting not only CNN-based object recognition but also MLP-based in-vehicle voice recognition. The AI processor integrates Super-Thread-Cores (STC) for neural network acceleration with function-safe general purpose cores that satisfy vehicular electronics safety requirements. The STC is composed of 16384 programmable nano-cores organized in a mesh-grid structured datapath network. Designed based on thorough analysis of neural network computations, the nano-core-in-memory architecture enhances computation intensity of STC with efficient feeding of multi-dimensional activation and kernel data into the nano-cores. The quad function-safe general purpose cores ensure functional safety of Super-Thread-Core to comply with road vehicle safety standard ISO 26262. The AI processor exhibits 32 Tera FLOPS, enabling hyper real-time execution of CNN, RNN, and FCN.
- KSP 제안 키워드
- Area constraints, Coupled with, Electronic systems, Functional Safety, High Speed, High performance, In-vehicle, Iso 26262, Low-Power, Memory architecture, Mesh structure