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Conference Paper
Implementation of Yolo-v2 Image Recognition and Other Testbenches for a CNN Accelerator
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- Authors
- Chan Kim, Hyun Mi Kim, Chun-Gi Lyuh, Yong Cheol Peter Cho, Jeongmin Yang, Jaehoon Chung, Kyoung Seon Shin, Jin Ho Han, Min-Seok Choi, In San Jeon, Young-Su Kwon
- Issue Date
- 2019-09
- Citation
- International Conference on Consumer Electronics (ICCE) 2019 : Berlin, pp.242-247
- Publisher
- IEEE
- Language
- English
- Type
- Conference Paper
- Abstract
- An implementation of Yolo-v2 image recognition and other testbenches for a deep learning accelerator is presented. This chip is the initial version of our on-going effort for a higher performance accelerator development. The accelerator is based on a systolic array and can handle convolution and max-pooling layer in a combined way or separately using 16 bit floating-point data. It also supports inner-product and LSTM layers. For demonstration and as one of the design verification testbenches, we implemented Yolo-v2 image recognition for 80 object classes. We converted the Yolo-v2 software to 16 bit floating point version and used it in the simulation and FPGA experiment during the chip development. Several other testbenches were designed and used to test various networks. In this paper, the accelerator's architecture and the Yolo-v2 implementation on our FPGA board including camera and LCD is explained, including the software implementation. Some analyses on the measured and estimated performance is shown.
- KSP Keywords
- Design Verification, Estimated performance, FPGA board, Floating-point data, Higher performance, Image recognition, Max-pooling, Systolic Array, deep learning(DL), software implementation