상세정보
학술지
High-Speed Hardware Architectures for ARIA with Composite Field Arithmetic and Area-Throughput Trade-Offs
- 발행일
- 200810
- 출처
- ETRI Journal, v.30 no.5, pp.707-717
- ISSN
- 1225-6463
- 출판사
- 한국전자통신연구원 (ETRI)
- 협약과제
- 08MC4200, 익명성 기반의 u지식정보보호기술 개발, 조현숙
- 초록
- This paper presents two types of high-speed hardware architectures for the block cipher ARIA. First, the loop architectures for feedback modes are presented. Areathroughput trade-offs are evaluated depending on the S-box implementation by using look-up tables or combinational logic which involves composite field arithmetic. The sub-pipelined architectures for non-feedback modes are also described. With loop unrolling, inner and outer round pipelining techniques, and S-box implementation using composite field arithmetic over GF(24)2, throughputs of 16 Gbps to 43 Gbps are achievable in a 0.25 μm CMOS technology. This is the first sub-pipelined architecture of ARIA for high throughput to date.
- KSP 제안 키워드
- CMOS Technology, Combinational logic, Composite field arithmetic, Hardware Architecture, High Speed, High throughput(HTP), Loop unrolling, Pipelined architecture, S-box, Trade-off, block cIPher