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Journal Article High-Speed Hardware Architectures for ARIA with Composite Field Arithmetic and Area-Throughput Trade-Offs
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Authors
Sang-Woo Lee, Sang-Jae Moon, Jeong-Nyeo Kim
Issue Date
2008-10
Citation
ETRI Journal, v.30, no.5, pp.707-717
ISSN
1225-6463
Publisher
한국전자통신연구원 (ETRI)
Language
English
Type
Journal Article
DOI
https://dx.doi.org/10.4218/etrij.08.0108.0194
Abstract
This paper presents two types of high-speed hardware architectures for the block cipher ARIA. First, the loop architectures for feedback modes are presented. Areathroughput trade-offs are evaluated depending on the S-box implementation by using look-up tables or combinational logic which involves composite field arithmetic. The sub-pipelined architectures for non-feedback modes are also described. With loop unrolling, inner and outer round pipelining techniques, and S-box implementation using composite field arithmetic over GF(24)2, throughputs of 16 Gbps to 43 Gbps are achievable in a 0.25 μm CMOS technology. This is the first sub-pipelined architecture of ARIA for high throughput to date.
KSP Keywords
CMOS Technology, Combinational logic, Composite field arithmetic, Hardware Architecture, High Speed, High throughput(HTP), Look up tables(LUTs), Loop unrolling, Pipelined architecture, S-box, Trade-off