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Journal Article 초저지연 제어를 위한 CPS 아키텍처 설계
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Authors
강성주, 전재호, 이준희, 하수정, 전인걸
Issue Date
2019-10
Citation
대한임베디드공학회논문지, v.14, no.5, pp.227-237
ISSN
1975-5066
Publisher
대한임베디드공학회
Language
Korean
Type
Journal Article
DOI
https://dx.doi.org/10.14372/IEMEK.2019.14.5.227
Abstract
Ultra-low latency control is one of the characteristics of 5G cellular network services, which means that the control loop is handled in milliseconds. To achieve this, it is necessary to identify time delay factors that occur in all components related to CPS control loop, including new 5G cellular network elements such as MEC, and to optimize CPS control loop in real time. In this paper, a novel CPS architecture for ultra-low latency control of CPS is designed. We first define the ultra-low latency characteristics of CPS and the CPS concept model, and then propose the design of the control loop performance monitor (CLPM) to manage the timing information of CPS control loop. Finally, a case study of MEC-based implementation of ultra-low latency CPS reviews the feasibility of future applications.
KSP Keywords
5G Cellular Networks, CPS architecture, Case studies, Concept model, Future applications, Latency control, Performance Monitor, Real-time, Time Delay, Ultra-low latency, control loop