상세정보
학술지
40-nm CMOS 공정을 이용한 220～260 GHz 대역 주파수 체배기 설계
- 저자
- 강동우
- 발행일
- 201911
- 출처
- 한국전자파학회논문지, v.30 no.11, pp.871-875
- ISSN
- 1226-3133
- 출판사
- 한국전자파학회 (KIEES)
- 협약과제
- 19HB2700, 멀티밴드 신호전송을 위한 다중 광채널 발생/조형 기술 개발, 송민협
- 초록
- In this paper, we present the design of a frequency doubler to generate a signal in the range of 220～260 GHz for 40-nm complementary metal oxide semiconductor(CMOS) technology. The circuit is composed of input, inter-change, and output matching as well as Marchand balun circuits in the form of microstrips. For an input frequency of 110～130 GHz, the doubler generates an output power between ?6.5 dBm and ?13 dBm with an output frequency of 220～260 GHz. The circuit consumes a power of only 0.66 mW with a supply voltage of 1.1 V. The dimensions of the chip, including pads, are 477μm× 486μm.
- KSP 제안 키워드
- 30 GHz, 60 GHz, Complementary metal-oxide-semiconductor(CMOS), Frequency doubler, Marchand Balun, Metal-oxide(MOX), Output frequency, Output power, Supply voltage, output matching