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Journal Article
Hardware Implementation and Analysis of Gen-Z Protocol for Memory-Centric Architecture
- Authors
- Seokbin Hong, Won-Ok Kwon, Myeong-Hoon Oh
- Issue Date
- 2020-07
- Citation
- IEEE Access, v.8, pp.127244-127253
- ISSN
- 2169-3536
- Publisher
- IEEE
- Language
- English
- Type
- Journal Article
- Abstract
- With the increase in memory-intensive applications, a memory-centric architecture has been proposed in which the central processing units (CPUs) access a pool of fabric-attached memory. This architecture eliminates the dependency of system components and provides benefits for achieving an independent upgrade cycle and fine-grained resource control. However, developing a memory-centric architecture requires new hardware and software for achieving the low-latency and high-bandwidth communication between the memory and the CPU. This paper presents a hardware prototype of a memory-centric architecture using Gen-Z, which is a new universal system interconnect optimized for ultralow latency and ultra-high bandwidth. The Gen-Z hardware prototype was designed according to the core specification 1.0a and implemented in two types of host interfaces. In this study, we measured the performance of the Gen-Z hardware prototype, i.e., the latency and throughput, and compared it with of the solid-state drive (SSD) and local memory. The experimental results indicated that the performance of remote memory access for a specific write request that utilizes the Gen-Z protocol was better than that of the SSD and local memory. Further, we discussed methods for improving the performance of the Gen-Z prototype.
- KSP Keywords
- Hardware Implementation, Hardware Prototype, Local memory, Low latency, Memory intensive, Memory-centric, Remote Memory Access, central processing unit, fine-grained, hardware and software, resource control
This work is distributed under the term of Creative Commons License (CCL)
(CC BY)
(CC BY)
