Random access preambles in 5G NR PRACH consist of Zadoff-Chu sequences. Modulo operation, which finds the remainder after division of one number by another, is one of the indispensable functions in ZC sequence generators. This paper proposes a scheme of modulo 139 calculation to reduce hardware complexity and offer 2 clock latency constantly. It requires 2 multipliers, one adder, one subtractor, and a 10-bit remover, which makes the hardware simple, fast, and offers constant latency because it excludes the use of divider in the hardware. Modulo operation is widely used in most digital signal processing. Although this paper especially focused on modulo 139, the proposed scheme shall apply modulo operations in various areas using divisor other than 139 as well.
KSP Keywords
Compact design, Digital Signal Processing, Hardware Complexity, Random Access Channel(RACH), Zadoff-Chu sequences, modulo operation
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