상세정보
학술지
8.2-GHz Band Radar RFICs for an 8 × 8 phased-array FMCW Receiver Developed with 65-nm CMOS Technology
- 발행일
- 202012
- 출처
- ETRI Journal, v.42 no.6, pp.943-950
- ISSN
- 1225-6463
- 출판사
- 한국전자통신연구원 (ETRI)
- 협약과제
- 19ZB1300, ICT 융합소자 핵심기술 개발, 송윤호
- 초록
- We propose 8.2-GHz band radar RFICs for an 8혻×혻8 phased-array frequency-modulated continuous-wave receiver developed using 65-nm CMOS technology. This receiver panel is constructed using a multichip solution comprising fabricated 2혻×혻2 low-noise amplifier phase-shifter (LNA-PS) chips and a 4ch RX front-end chip. The LNA-PS chip has a novel phase-shifter circuit for low-voltage operation, novel active single-to-differential/differential-to-single circuits, and a current-mode combiner to utilize a small area. The LNA-PS chip shows a power gain range of 5혻dB to 20혻dB per channel with gain control and a single-channel NF of 6.4혻dB at maximum gain. The measured result of the chip shows 6-bit phase states with a 0.35?? RMS phase error. The input P1 dB of the chip is approximately ??27.5혻dBm at high gain and is enough to cover the highest input power from the TX-to-RX leakage in the radar system. The gain range of the 4ch RX front-end chip is 9혻dB to 30혻dB per channel. The LNA-PS chip consumes 82혻mA, and the 4ch RX front-end chip consumes 97혻mA from a 1.2혻V supply voltage. The chip sizes of the 2혻×혻2 LNA-PS and the 4ch RX front end are 2.39혻mm혻×혻1.3혻mm and 2.42혻mm혻×혻1.62혻mm, respectively.
- KSP 제안 키워드
- CMOS Technology, Current-mode(CM), Frequency-Modulated Continuous Wave(FMCW), Front-End, GHz band, Gain Control, Input power, Low voltage operation, Phase Shifter, Power gain, Radar System
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