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Journal Article
A dual‐path high linear amplifier for carrier aggregation
- Authors
- Dong-Woo Kang, Jang-Hong Choi
- Issue Date
- 2020-10
- Citation
- ETRI Journal, v.42, no.5, pp.773-780
- ISSN
- 1225-6463
- Publisher
- 한국전자통신연구원 (ETRI)
- Language
- English
- Type
- Journal Article
- Abstract
- A 40혻nm complementary metal oxide semiconductor carrier-aggregated drive amplifier with high linearity is presented for sub-GHz Internet of Things applications. The proposed drive amplifier consists of two high linear amplifiers, which are composed of five differential cascode cells. Carrier aggregation can be achieved by switching on both the driver amplifiers simultaneously and combining the two independent signals in the current mode. The common gate bias of the cascode cells is selected to maximize the output 1혻dB compression point (P1dB) to support high-linear wideband applications, and is used for the local supply voltage of digital circuitry for gain control. The proposed circuit achieved an output P1dB of 10.7혻dBm with over 22.8혻dBm of output 3rd-order intercept point up to 0.9혻GHz and demonstrated a 55혻dBc adjacent channel leakage ratio (ACLR) for the 802.11af with ?닋5혻dBm channel power. To the best of our knowledge, this is the first demonstration of the wideband carrier-aggregated drive amplifier that achieves the highest ACLR performance.
This work is distributed under the term of Korea Open Government License (KOGL)
(Type 4: : Type 1 + Commercial Use Prohibition+Change Prohibition)
(Type 4: : Type 1 + Commercial Use Prohibition+Change Prohibition)
