상세정보
학술대회
Verification of Interconnect RTL Code for Memory-Centric Computing using UVM
- 발행일
- 202102
- 출처
- International Conference on Electronics, Information and Communication (ICEIC) 2021, pp.861-864
- 협약과제
- 20HS2700, 메모리 중심 차세대 컴퓨팅 시스템 구조 연구, 오명훈
- 초록
- This document is about the verification of an interconnect (i.e. switch) RTL code that is based on Gen-Z protocol using Universal Verification Methodology (UVM). Ports in the switch for transmission packets are connected to virtual interfaces with UVM. The packets that are generated in the UVM environment are transmitted into the ports of the switch through the virtual interfaces. For verifying the switch logic, we designed sequence items and a virtual sequencer and simulated it.
- KSP 제안 키워드
- Universal verification methodology(UVM), memory-centric computing, switch logic