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학술대회 CNPC Deinterleaver Implementation to Increase Hardware Logic Utilization on FPGA
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저자
문권한, 김희욱, 김대호
발행일
202104
출처
International Conference on Artificial Intelligence in Information and Communication (ICAIIC) 2021, pp.385-389
DOI
https://dx.doi.org/10.1109/ICAIIC51459.2021.9415239
초록
The UAV has been used in various fields, and is gradually expanding its application fields. To safely operate the UAV, the stable communication system for command is standardized in RTCA and the standardization is described in MOPS. In MOPS, transmitter uses interleaver module as the one of the components. This interleaver module is used to avoid the burst errors in transmission. Use of interleaver module in transmitter, requires deinterleaver to reorder the shuffled transmitter signal. To implement this module in the real world, the FPGA is used as the hardware. The implementation on FPGA requires for developers to understand the parallel processing. Moreover, deinterleaver accepts the symbol with multi bit as the input. This means that a lot of RAM has to be used for the deinterleaver matrix. To implement a module requiring a lot of RAMs, FPGA uses BRAMs despite the situation where LUT RAMs remain. To develop deinterleaver module utilizing LUT RAMs as possible in the FPGA, this paper introduces the timing diagram for the scheme.
키워드
BRAM, CNPC, Deterleaver module, FPGA, Interleaver module, LUT RAM, Parallel processing, Timing diagram, UAV
KSP 제안 키워드
Application fields, Communication system, Parallel Processing, Real-world, burst errors