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학술대회 Timing Diagram for CNPC Interleaver Implementation on FPGA
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저자
문권한, 강군석, 김대호
발행일
202104
출처
International Conference on Artificial Intelligence in Information and Communication (ICAIIC) 2021, pp.381-384
DOI
https://dx.doi.org/10.1109/ICAIIC51459.2021.9415266
초록
The command and non-payload communication has been standardized to reliably control the UAV over 150kg in RTCA. This standardization was described in MOPS. In MOPS, transmitter uses the interleaver module as the one of components. This interleaver module is used to overcome the burst errors in transmission. The implementation in FPGA is hard since FPGA requires the understanding of parallel processing. To implement this module using parallel processing, the state of each variable should be described according to the timing. This paper shows the timing diagram of our implementation to provide a solution for CNPC interleaver module.
KSP 제안 키워드
Burst error, Parallel Processing