BROWSE
Detail
Conference Paper
Timing Diagram for CNPC Interleaver Implementation on FPGA
Cited 0 time in 
Share 
Share
- Authors
- GwonHan Mun, KunSeok Kang, DeaHo Kim
- Issue Date
- 2021-04
- Citation
- International Conference on Artificial Intelligence in Information and Communication (ICAIIC) 2021, pp.381-384
- Language
- English
- Type
- Conference Paper
- Abstract
- The command and non-payload communication has been standardized to reliably control the UAV over 150kg in RTCA. This standardization was described in MOPS. In MOPS, transmitter uses the interleaver module as the one of components. This interleaver module is used to overcome the burst errors in transmission. The implementation in FPGA is hard since FPGA requires the understanding of parallel processing. To implement this module using parallel processing, the state of each variable should be described according to the timing. This paper shows the timing diagram of our implementation to provide a solution for CNPC interleaver module.
- KSP Keywords
- Parallel Processing, burst errors