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Conference Paper 차세대 신경망 SNN core 반도체 설계
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Authors
오광일, 김성은, 강태욱, 김혁, 이재진
Issue Date
2021-07
Citation
대한전자공학회 학술 대회 (하계) 2021, pp.2287-2288
Publisher
대한전자공학회
Language
Korean
Type
Conference Paper
Abstract
This paper introduces a low-power SNN core chip using analog circuit scheme and its inference operation for reduced MNIST pattern. After summarizing the features of SNN core chip, an experimental result will be shown as a simple inferencing task.
KSP Keywords
Experimental Result, Low-Power, analog circuits, core chip