상세정보
학술지
In Situ Implementation of Silicon Epitaxial Layer on Amorphous SiO 2 Using Reduced-pressure Chemical Vapor Deposition
- 발행일
- 202109
- 출처
- Applied Materials Today, v.24, pp.1-7
- ISSN
- 2352-9407
- 출판사
- Elsevier
- 협약과제
- 21JB2900, 벌크 CMOS 기반의 reconfigurable FET 핵심기술 개발 , 서동우
- 초록
- With the increasing power demand of system-on-chip structures, an ultrathin body is increasingly important owing to its low power leakage; silicon-on-insulator (SOI) technology is used to fabricate such ultrathin platforms. However, the contemporary SOI process and the wafer itself are complex and expensive. In this study, we developed an easy SOI fabrication process that can be implemented on any desired local area of a bulk silicon wafer using the commercially implemented reduced-pressure chemical vapor deposition technique. A local SOI was fabricated through the selective epitaxial growth of silicon, which can also be grown laterally on top of amorphous SiO2 patterned with a 1 μm-wide silicon seed zone and an etch stopper with dimensions of 20 × 100 μm. The local SOI, processed to a thickness of 100 nm or less by chemical mechanical polishing, exhibited a highly crystalline state, as confirmed by cross-sectional imaging and diffraction pattern analysis, surface roughness analysis, and wide-range epitaxy analysis. The local SOI exhibited a surface roughness of 0.237 nm and maintained a perfect (100) crystal plane, identical to that of the silicon wafer, under optimized process conditions. We successfully fabricated reconfigurable transistors on the present local SOI, which implies that contemporary silicon electronics can take advantage of SOI devices on its own platform.
- KSP 제안 키워드
- Chemical Mechanical Polishing(CMP), Chemical Vapor Deposition, Crystal plane, Crystalline state, Deposition technique, Low Power Leakage, Optimized process, Power Demand, Process conditions, SOI process, Selective epitaxial growth(SEG)
본 저작물은 크리에이티브 커먼즈 저작자 표시 - 비영리 - 변경금지 (CC BY NC ND) 조건에 따라 이용할 수 있습니다.
