상세정보
학술대회
Design of Low-latency Synthesizable PUCCH Demodulation Unit Using Simulink HDL Coder
- 발행일
- 202110
- 출처
- International Conference on Information and Communication Technology Convergence (ICTC) 2021, pp.1387-1389
- 협약과제
- 21HH1400, 동적 기능분할을 지원하는 개방형 기지국 분산 유닛(DU) 기술 개발, 이문식
- 초록
- Low-latency synthesizable demodulation unit for 5G-NR Physical Uplink Control Channel (PUCCH) Format 0 is designed using Simulink Hardware Description Language (HDL) Coder. The modulated sequence of PUCCH Format 0 is generated by a sequence group number and cyclic shift value depending on many higher-layer parameters and scheduling parameters. However, high-latency of the sequence generator comes from the computation of the group number and cyclic shift value. In this paper, the efficient architecture is introduced for the sequence generator for the low-latency synthesizable demodulation unit and verified under the FPGA-in-the-loop (FIL) workflow using Simulink HDL Coder and Xilinx ZCU102 evaluation board. This approach is useful to provide validation before hardware implementation.
- KSP 제안 키워드
- Cyclic shift, FPGA-In-the-Loop, HDL Coder, Hardware Implementation, Low latency, Physical uplink control channel, efficient architecture, hardware description language(HDL), sequence generator