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Conference Paper
Design of Low-latency Synthesizable PUCCH Demodulation Unit Using Simulink HDL Coder
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- Authors
- Young-Hoon Kim, Hyungsik Ju, Ik-Jae Chun, Chan Bok Jeong, Moon-Sik Lee
- Issue Date
- 2021-10
- Citation
- International Conference on Information and Communication Technology Convergence (ICTC) 2021, pp.1387-1389
- Publisher
- IEEE
- Language
- English
- Type
- Conference Paper
- Abstract
- Low-latency synthesizable demodulation unit for 5G-NR Physical Uplink Control Channel (PUCCH) Format 0 is designed using Simulink Hardware Description Language (HDL) Coder. The modulated sequence of PUCCH Format 0 is generated by a sequence group number and cyclic shift value depending on many higher-layer parameters and scheduling parameters. However, high-latency of the sequence generator comes from the computation of the group number and cyclic shift value. In this paper, the efficient architecture is introduced for the sequence generator for the low-latency synthesizable demodulation unit and verified under the FPGA-in-the-loop (FIL) workflow using Simulink HDL Coder and Xilinx ZCU102 evaluation board. This approach is useful to provide validation before hardware implementation.
- KSP Keywords
- Cyclic shift, Efficient architecture, FPGA-in-the-Loop, HDL Coder, Hardware description Language(HDL), Hardware implementation, Low latency, Physical uplink control channel, sequence generator