상세정보
학술지
Analysis of Temporal Carrier Build-up in Reconfigurable Field-effect Transistor
- 발행일
- 202201
- 출처
- Electronics Letters, v.58 no.1, pp.35-37
- ISSN
- 0013-5194
- 출판사
- IET
- 협약과제
- 21JB2900, 벌크 CMOS 기반의 reconfigurable FET 핵심기술 개발 , 서동우
- 초록
- Based on the analysis of the carrier density change of a symmetric gate reconfigurable field-effect transistor that can operate p- or n-type transistors in an integrated circuit (IC), its unique limiting factor, carrier build-up time, is quantitatively derived for operating speed in addition to conventional resistance and capacitance (RC) and transit time effect. Originating from the characteristic of carrier confinement in a channel between two Schottky potential barriers, the carrier build-up time for the operation could take up to ~1000 times longer than the transit time across the channel.
- KSP 제안 키워드
- Build-up time, Carrier density, Density change, Field-effect transistors(FETs), Integrated circuit, Limiting factors, Operating speed, Potential barrier, Time effect, Transit time, carrier confinement
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