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Conference Paper
FPGA-Based Ordered Statistic Decoding Architecture for B5G/6G URLLC IIOT Networks
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- Authors
- Changhyeon Kim, Dongyoung Rim, Jeongwon Choe, Dongyun Kam, Giyoon Park, Seokki Kim, Youngjoo Lee
- Issue Date
- 2021-11
- Citation
- Asian Solid-State Circuits Conference (A-SSCC) 2021, pp.1-3
- Language
- English
- Type
- Conference Paper
- Abstract
- The ordered statistic decoding (OSD) approach for short-length BCH codes has been continuously considered as one of the promising error-correction codes by achieving a block error rate (BLER) of less than 10^{-6}, which is attractive to the ultra-reliable and low-latency communication (URLLC) for industrial IoT (IIOT) solutions [1], [2]. However, it is hard to directly realize the conventional OSD algorithm because of the compute-intensive Gaussian elimination and iterative reprocessing steps. Based on the recent segmentation discarding decoding (SDD) approach [3], in this work, we newly present an ultralow-latency OSD architecture reducing the decoding latency by 12 times, which is implemented at an FPGA-based verification platform.
- KSP Keywords
- BCH codes, Block Error Rate, Error Correction Code(ECC), Gaussian elimination, Industrial IoT, Low-Latency Communication, Short-length, compute-intensive