상세정보
학술대회
FPGA-Based Ordered Statistic Decoding Architecture for B5G/6G URLLC IIOT Networks
- 발행일
- 202111
- 출처
- Asian Solid-State Circuits Conference (A-SSCC) 2021, pp.1-3
- 협약과제
- 21HH1200, 셀룰러 기반 산업 자동화 시스템 구축을 위한 5G 성능 한계 극복 저지연, 고신뢰, 초연결 통합 핵심기술 개발, 신재승
- 초록
- The ordered statistic decoding (OSD) approach for short-length BCH codes has been continuously considered as one of the promising error-correction codes by achieving a block error rate (BLER) of less than 10^{-6}, which is attractive to the ultra-reliable and low-latency communication (URLLC) for industrial IoT (IIOT) solutions [1], [2]. However, it is hard to directly realize the conventional OSD algorithm because of the compute-intensive Gaussian elimination and iterative reprocessing steps. Based on the recent segmentation discarding decoding (SDD) approach [3], in this work, we newly present an ultralow-latency OSD architecture reducing the decoding latency by 12 times, which is implemented at an FPGA-based verification platform.
- KSP 제안 키워드
- BCH codes, Block Error Rate(BLER), Error Correction Codes, Gaussian Elimination, Low-Latency Communication, Short-length, compute-intensive, industrial IoT