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A 3.1–10.6 GHz RF receiver front-end in 0.18 um CMOS for ultra-wideband applications
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- Authors
- B. Park, K. Lee, S. Choi, S. Hong
- Issue Date
- 2010-05
- Citation
- Advances in Communication, Radar, Sensor and Measurement Systems (IMS) 2010, pp.1-1
- Language
- English
- Type
- Conference Paper
- Abstract
- A fully integrated 0.18-μm CMOS receiver frontend for UWB system is implemented. This receiver enables 11 bands of operation covering 3.1 to 10.6-GHz with embedding a tunable notch filter to eliminate interferer at 5-GHz wireless local area network (WLAN). The receiver consists of a zero-IF receive chain and linearity specification is discussed. It is composed of a single-ended low noise amplifier (LNA), a down-conversion mixer, a low pass filter (LPF), and a programmable gain amplifier (PGA) with 10 buffer. The LNA employs a common-gate topology of 1st stage with dual-resonant loads, a cascode amplifier of 2nd stage for mid-band resonance and tunable notch filter. The down-conversion mixer adopts single-balanced architecture with LO cancellation. The LPF is implemented based on active RC topology, also implements a 4-stage programmable gain amplifier. The receiver dissipates 49.3 rnA from 1.8 V power supply. The average conversion gain of receiver IC is 73.5 dB and system noise figure is 8.4 dB. Input PldB increase from -36.8 dBm at 4- GHz to -30.5 dBm at 10.3-GHz. The attenuation is 8.5 dB achieved in interference rejection band at 5.2-GHz. It occupies an area of 0.98 mm × 3.3 mm including the bond pads. © 2010 IEEE.
- KSP Keywords
- 0.18um CMOS, 6 GHz, CMOS Receiver, Cascode amplifier, Conversion gain, Down-conversion mixer, Interference Rejection, Low pass filter(LPF), RF receiver front-end, Single-Ended, Single-balanced