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학술대회 A 9.15mW 0.22mm2 10b 204MS/s pipelined SAR ADC in 65nm CMOS
Cited 40 time in scopus Download 6 time Share share facebook twitter linkedin kakaostory
저자
전영득, 조영균, 남재원, 김귀동, 이우열, 홍국태, 권종기
발행일
201009
출처
Custom Integrated Circuits Conference (CICC) 2010, pp.1-4
DOI
https://dx.doi.org/10.1109/CICC.2010.5617457
협약과제
10MB1700, 45nm급 혼성 SoC용 아날로그 회로기술, 권종기
초록
This paper describes a 10b 204MS/s analog-to-digital converter (ADC) employing a pipelined successive approximation register (SAR) architecture for low power consumption and small area. To improve the operation frequency, the pipelined SAR ADC consists of two channels with a proposed asynchronous timing technique. This technique increases the amplification time of a residue opamp. To reduce power and area, the opamp is shared between two channels. A reference buffer with a deglitch circuit reduces the glitch and settling time of reference voltages. The prototype ADC fabricated in a 65nm CMOS process shows a SNDR of 55.2dB and a SFDR of 63.5dB with a 2.4MHz input at 204MS/s. The ADC occupies 0.22mm2 and dissipates 9.15mW at a 1.0V supply. The FoM of the ADC is 95.4fJ/conversion-step. © 2010 IEEE.
KSP 제안 키워드
65nm CMOS, Analog to digital converter(ADC), CMOS Process, Small area, Successive Approximation(SA), low power consumption, pipelined SAR ADC, reference buffer, settling time, successive approximation analog-to-digital converter(SAR ADC), successive approximation register