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A Novel TFT with a Laterally Engineered Bandgap for of 3D Logic and Flash Memory
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- Authors
- Sung-Jin Choi, Jin-Woo Han, Sung Ho Kim, Dong-Il Moon, Moon Gyu Jang, Yang-Kyu Choi
- Issue Date
- 2010-06
- Citation
- Symposium on VLSI Technology (VLSIT) 2010, pp.111-112
- Language
- English
- Type
- Conference Paper
- Abstract
- A dopant segregated Schottky barrier (DSSB) TFT SONOS device is demonstrated for the application of 3D TFT logic devices and flash memory. To apply the DSSB to 3D TFT flash memory, a novel spacer-free structure is successfully implemented. The DSSB TFT SONOS shows a good distribution of programmed VT by one-time programming with high-speed (a V T shift of 2.9 V @ 32 ns) due to the use of a unique local injection of carriers from the DSSB S/D junctions and it is not affected by grain boundaries. Moreover, the program speed is accelerated by reduction of the fin width owing to the enhanced field. © 2010 IEEE.
- KSP Keywords
- Enhanced field, FLASH memory, Fin width, Free structure, Grain Boundaries, High Speed, Schottky barrier, V t, dopant segregated, logic devices