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Journal Article NPU 반도체를 위한 저정밀도 데이터 타입 개발 동향
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Authors
김혜지, 한진호, 권영수
Issue Date
2022-02
Citation
전자통신동향분석, v.37, no.1, pp.53-63
ISSN
1225-6455
Publisher
한국전자통신연구원
Language
Korean
Type
Journal Article
DOI
https://dx.doi.org/10.22648/ETRI.2022.J.370106
Abstract
With increasing size of transformer-based neural networks, a light-weight algorithm and efficient AI accelerator has been developed to train these huge networks in practical design time. In this article, we present a survey of state-of-the-art research on the low-precision computational algorithms especially for floating-point formats and their hardware accelerator. We describe the trends by focusing on the work of two leading research groups-IBM and Seoul National University-which have deep knowledge in both AI algorithm and hardware architecture. For the low-precision algorithm, we summarize two efficient floating-point formats (hybrid FP8 and radix-4 FP4) with accuracy-preserving algorithms for training on the main research stream. Moreover, we describe the AI processor architecture supporting the low-bit mixed precision computing unit including the integer engine.
KSP Keywords
Accuracy-preserving, Computational algorithm, Design time, Floating point, Hardware Architecture, Hardware accelerator, Low-precision, Mixed precision, Practical design, Processor architecture, Radix-4
This work is distributed under the term of Korea Open Government License (KOGL)
(Type 4: : Type 1 + Commercial Use Prohibition+Change Prohibition)
Type 4: