ETRI-Knowledge Sharing Plaform

KOREAN
논문 검색
Type SCI
Year ~ Keyword

Detail

Conference Paper Releasing the Memory Bottleneck to Display Video Correctly
Cited 0 time in scopus Share share facebook twitter linkedin kakaostory
Authors
Hyeonguk Jang, Sukho Lee, Jae-Jin Lee, Kyuseung Han
Issue Date
2022-10
Citation
International SoC Design Conference (ISOCC) 2022, pp.340-341
Publisher
IEEE
Language
English
Type
Conference Paper
DOI
https://dx.doi.org/10.1109/ISOCC56007.2022.10031379
Abstract
Applications with video output require large memory bandwidth for SoCs. The memory is easy to become a bottleneck, failing to meet the hard real-time constraints of video display. Thus, in this paper, we propose SoC architecture to ensure the proper display by releasing the memory bottleneck. The proposed architecture is designed at register-transfer level, and is verified using Xilinx FPGA. Experiments show that the FPGA prototype successfully solves the incorrect display problem.
KSP Keywords
FPGA prototype, Hard real-time, Large memory, Memory bandwidth, Memory bottleneck, Real-time constraints, Register Transfer Level(RTL), SOC architecture, Xilinx FPGA