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Conference Paper
Releasing the Memory Bottleneck to Display Video Correctly
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- Authors
- Hyeonguk Jang, Sukho Lee, Jae-Jin Lee, Kyuseung Han
- Issue Date
- 2022-10
- Citation
- International SoC Design Conference (ISOCC) 2022, pp.340-341
- Publisher
- IEEE
- Language
- English
- Type
- Conference Paper
- Abstract
- Applications with video output require large memory bandwidth for SoCs. The memory is easy to become a bottleneck, failing to meet the hard real-time constraints of video display. Thus, in this paper, we propose SoC architecture to ensure the proper display by releasing the memory bottleneck. The proposed architecture is designed at register-transfer level, and is verified using Xilinx FPGA. Experiments show that the FPGA prototype successfully solves the incorrect display problem.
- KSP Keywords
- FPGA prototype, Hard real-time, Large memory, Memory bandwidth, Memory bottleneck, Real-time constraints, Register Transfer Level(RTL), SOC architecture, Xilinx FPGA